http://www.obdev.at/products/avrusb/prjhid.html
http://avrusb.wikidot.com/hardware
http://www.cesko.host.sk/IgorPlugUSB_RS232/IgorPlug-USB%20(AVR)%20RS232_eng.htm
some idea for temp reading
http://www.harbaum.org/till/i2c_tiny_usb/index.shtml
http://www dot i c 3 7 dot com/icasp/info dot asp?inqure_leaveword=49
looking for quotation, 8 pin DIP ATTINY45-20PU
好久以前看過, Atmel 的 AVR 系列的 RISC MCU, 用 IO 模擬 USB 1.1 (bit rate 1.5Mhz = 1/1.5us = 0.67us 傳輸一個 0 或 1), 解決低速低資料量的應用, 並且不需要特別的 USB 專用模組或 MCU 本身完全不需要有 USB 功能, 只要 MCU 的速度夠高便可以.
成功嚐試過以 HC05 的 IO 模擬 RS232, 接收部分以 INTERRUPT 啟動, 發送部份完全自由. 不知道可否再次以 HC08 模擬 USB 1.1.
比較 RS232 的連線方法
了解 USB 1.1 每個封包的長度, 最長據說是 11 BYTE
以下的網址, 標示 LOW SPEED 1.5Mbits/s ±1.5% 或 15,000ppm, 也就是等同於 0.67us ±1.5% 的時間內收發每個 0 或 1,
http://www.beyondlogic.org/usbnutshell/
USB封包內, LSB先行
LSB / MSB 舉例, 如果要傳送 1100 四個 bit,
LSB先行的順序是從右到左, 0, 0, 1, 1
MSB先行的順序是從左到右, 1, 1, 0, 0
USB 封包共有四種
Token Packets
Data Packets
Handshake Packets
Start of Frame Packets
計算所得, LOW SPEED, 最長封包大約 12 BYTE
換算 Packet ID Value, 4 bit 加上互補後的 4 bit, 組成完整的 8 bit Packet ID (PID).
每次USB DEVICE 插到電腦時, 電腦 (HOST) 依據不同的 D- 或 D+ 訊號線上面的電壓, 判斷插進來的到底是啥東東, 分辨 LOW / FULL / HIGH 三種不同速度的DEVICE.
除了自己寫, 也可以看看人家的描述
http://topamp.blogspot.com/2007/11/usb-2.html
http://macetech.com/blog/?q=node/46
電氣特性, 差分輸入輸出, 以 D+ 及 D- 作表示,
如果控制或讀取以兩條IO分別代表的 D+ 及 D-, 只有四種組合, 00, 01, 10, 11, 除了 11外, 00表示SE0, 01表示0, 10表示1
| Bus State | Levels | ||
| D+ | D- | ||
| Differential '1' | D+ high, D- low | H | L |
| Differential '0' | D- high, D+ low | L | H |
| Single Ended Zero (SE0) | D+ and D- low | L | L |
| Single Ended One (SE1) | D+ and D- high | H | H |
| Data J State: | |||
| Low-speed | Differential '0' | L | H |
| Full-speed | Differential '1' | H | L |
| Data K State: | |||
| Low-speed | Differential '1' | H | L |
| Full-speed | Differential '0' | L | H |
| Idle State: | |||
| Low-speed | D- high, D+ low, Differential '0' | L | H |
| Full-speed | D+ high, D- low, Differential '1' | H | L |
| Resume State | Data K state | ||
| Start of Packet (SOP) | Data lines switch from idle to K state | ||
| End of Packet (EOP) | SE0 for 2 bit times followed by J state for 1 bit time | ||
| Disconnect | SE0 for >= 2us | ||
| Connect | Idle for 2.5us | ||
| Reset | SE0 for >= 2.5 us | ||
| http://www.usbmadesimple.co.uk/ums_3.htm | |||
根據如下的描述 (http://www.obdev.at/developers/articles/00003.html),
* USB 採用 NRZI 的編碼 (http://en.wikipedia.org/wiki/Non-return-to-zero#Non-Return-to-Zero_Inverted_.28NRZI.29), 意思是, 是次讀取D+D-, 如果維持如上次取樣的狀態, 表示為1, 否則為0.
* 例外的是, 假如連續出現6次1, 則會加入一位0, 接收端需要把這個0去除, 稱作 Bitstuff decoding.
* USB 封包結束標誌, D+和D-都為邏輯0或0電壓 (只適用於LOW SPEED), 稱作SE0, 持續2 BIT的時間
如果以CISC CPU的速度, 就算OVERCLOCK到9MHz, 每BIT的處理時間, 只有6個CPU CLOCK CYCLE, 很難達到以軟體接收的和即時解碼的要求, 除非CPU的速度提高到20-30MHz. 但是以9MHz這樣的速度, 單獨執行軟體接收而不即時解碼, 應該很容易就做到, 因為最多的條件跳轉判定, 如BRCLR / BRSET, 需要[5]個CPU CYCLE, 假如以INT的IO作為接收點, 以INTERRUPT SERVICE ROUTINE同步接收, 應該跟RS232的接收方法一樣, 不同的只是時間會更加緊湊.
| HC08 | cycle time (uS) | |
| OSC (MHz) | 32 | 0.031 |
| CPU speed (MHz max) | 9 | 0.111 |
| USB speed | 1.5 | 0.667 |
| CPU cycle / USB bit | 6.000 | |
| CPU cycle / USB byte | 48.000 |
再來考慮時間的關鍵性, USB的資料封包都是以NRZI編碼後及差分信號傳送的SYNC作為開頭, 8 BIT資料的傳送順序是從左到右的 (10101000), 所以, 如果直接以1.5Mbit/sec的速度直接讀取 D-上的資料, 應該可以收到10101000, 然後直接儲存這8 BIT (或一個BYTE) 的資料備用, 或許可以達成稍後的解碼目標. 另外, 假如發送端會在發出連續6個1後面, 額外多插入一個0 (STUFFING BIT), 以接收端來看, 紀錄14 BYTE的資料, 除了SYNC的一個BYTE, 有可能包含最多不超過13個STUFFING BIT, 大約2BYTE, 所以, 發送端如果要輸出14 BYTE資料, 以USB NRZI發送後, 接收端有可能收到14+2BYTE資料, 包括SYNC, 13 BYTE資料和大約2 BYTE 的 STUFFING BIT.
一個比較粗糙的作法, 嚐試接收 SYNC PATTERN, 僅1 BYTE長度做試驗, 共需要48 CPU CYCLE, 剛剛好滿足接受1 BYTE的時間要求.
****************************************************************
* IRQ Handlers - used to detect the USB packet, *
* CPU overclock to 9MHz *
* 1.5Mbit/sec = 6 CPU cycle
* USB bus Idel state (Low spped, J state), D- = high, D+ = low
* Idle state - The state of the data lines when the pulled up
* line is high, and the other line is low,. This is
* the state of the lines before and after a packet is sent.
*
* D- = PTA2 (INT0) (HC908QT series)
* D+ = PTA0
****************************************************************
.list
.Cycle_Adder_On
IRQ_handler: ; D- = PTA2 = IRQ pin, response latency, CPU cycle, TBA
check_USB_SYNC: ; USB SYNC pattern is 10101000, seen on D-
bit1_of_SYNC:
sei ; [2] disable INT0, inhibit pulse chain cause other INT0 re-entry
brclr 0,PORTA,not_SE0 ; [5] check D+, since D- is low already
; both lines are LOW, it is SE0, End Of Packet
; 1st bit time pass, and costed 1 more CPU CYCLE
bit2_of_SYNC:
brset 2,PORTA,$+3 ; [5] D- should be H of SYNC 2nd bit, next instruction anyway
;nop ; [1], remark this, recover one CPU cycle lost at 1st bit check with SEI instruction
bit3_of_SYNC:
brclr 2,PORTA,$+3 ; [5] D- should be L of SYNC 3rd bit, next instruction anyway
nop ; [1]
bit4_of_SYNC:
brset 2,PORTA,$+3 ; [5] D- should be H of SYNC 4th bit, next instruction anyway
nop ; [1]
bit5_of_SYNC:
brclr 2,PORTA,$+3 ; [5] D- should be L of SYNC 5th bit, next instruction anyway
nop ; [1]
bit6_of_SYNC:
brset 2,PORTA,$+3 ; [5] D- should be H of SYNC 6th bit, next instruction anyway
nop ; [1]
bit7_of_SYNC:
brclr 2,PORTA,$+3 ; [5] D- should be L of SYNC 7th bit, next instruction anyway
nop ; [1]
bit8_of_SYNC:
brclr 2,PORTA,$+3 ; [5] D- should be L of SYNC 8th bit, next instruction anyway
nop ; [1]
.Cycle_Adder_Off
;when all instruction has been pass through, the time of SYNC BYTE is elasped precisely.
not_SE0:
rti
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